High clock rates and high frequencies
Digital electronic systems need increasingly complex interconnections between primary switching devices i.e. the transistors, and the user interface. Clocking rates of ICs are well into the low gigahertz region. Yet, the communication bandwidth outside and between chips remains an order of magnitude lower and prevent the full utilization of the chips potential. Another factor that can no longer be ignored, is that a large amount of power dissipation in high-speed integrated circuits comes from the I/O drivers and interconnect lines between chips. Most IC designers' efforts have concentrated on reducing the power required by the chip logic, while little has been done to date to improve power dissipation in the interconnect circuitry.
WLP and placing the bumps over the polymer are key elements in easing the interchip bus speed bottleneck as well as minimizing power dissipation. WLP has important advantages. Primarily, it shortens the length of the interconnect, a major benefit for high speed because it minimizes the interconnect parasitic capacitance. This is a direct benefit of placing the bumps over a thick layer of polymer. In addition, this technology offers the ability to control the impedance of the transmission lines.
To illustrate the need for speed, an article dated Feb 27, 2003 in the consumer oriented PC Magazine features alleged "confidential Intel documents" revealing Intel's roadmap involving flip-chips. Note that in effect this technology has been published by Intel some time ago but now reaches outside of the engineering community.
PC bus speeds are expected to increase to 800 MHz in the next 4 to 5 years to face the present bottleneck occuring outside of the semiconductor dies. With clock rates well in the GHz region for the past years, the PCs are using comparatively crippingly low bus speeds in the low hundreds MHz. Intel is paving the way for improved technology which will better match their semiconductor chip clocking rates. The anticipated bus speeds will require matched and controlled impedance in the circuit boards and their interfaces.
"Tejas", the successor to the Pentium 4-style "Prescott" processor, will officially launch in the second half of 2004 and will include the Flip-Chip Technology on Organic Pin Grid Array Packages developed a couple of years ago and publicized in the 3rd quarter 2000 issue of the Intel Technology Journal. The article is entitled "Flip-Chip Technology on Organic Pin Grid Array Packages" and shows the use of C4 bumped dies.