Electrical Design

Clocking speeds of digital devices and operating frequencies of analog systems keep increasing. This is a benefit directly derived from shrinking of the semiconductor geometries. The continual decrease in minimum feature sizes has enabled picosecond risetime in switching transistors, in addition to the placement of billions of active components on a single wafer. Now, the urgency is to improve data communication in and out of the chips in order to use their capabilities effectively. Packaging engineers are responsible for improving the communication bandwidth between chips.

In fact the bandwidth bottleneck starts at the bond pads. Billions of wire or ribbon bonds operate at microwave frequencies in MICs (Microwave Integrated Circuits) but ... the bonds are extremely short in order to keep the inductance down. It is impossible to use the same techniques with microprocessors or other high clock rates ICs with a large number of I/Os because the key is short connections for high frequencies. It follows that the first interconnect level has to rely on low parasitic impedance solder bumps and redistribution layers on the wafer.

A decade ago, bumping was still done primarily for its gang joining ability and capability to accommodate very large number of I/Os. Few advanced devices were built using HDMI (High Density Multilayer Interconnect) techniques and required bumping for its electrical characteristics.

Redistribution layer (RDL)

Placing interconnect lines over silicon wafers requires careful consideration of the wafers properties. Because silicon is a semiconductor, interconnect lines couple with the mobile charges in the wafer. The capacitance of the interconnect lines can be significant and cut down the frequency response of the system. See for instance the paper authored by NIST's scientists R. B. Marks and D. F. Williams, "Accurate electrical characterization of high-speed interconnections," Proceedings, 1994 International Symposium on Microelectronics, pp. 96-101, Nov. 1994.

Terminating a redistribution layer directly over the standard SiO2or Si3N4 passivation layer will give poor high frequency response. Because of the coupling into the silicon, it is necessary to place bumps over a thick low dielectric constant layer hence fabricating bumps-on-polymer (BOP) structures.

Our experience in designing interconnect circuits over silicon may save you costly iterations. We have done physical design and implementation of transmission lines over silicon wafers for the past 15 years. We fabricated parts with up to six superposed metallization layers, and many circuits were then far more complex than an RDLs design will ever be. We have designed RDLs for special applications, such as circuits incorporating low noise analog blocks, surrounded by digital circuitry. This type of circuit requires separate analog and digital grounds.